1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM), and particularly to a checkerboard deep trench DRAM cell array layout.
2. Description of the Prior Art
As various consumer electronic products are constantly miniaturized, the size of the semiconductor devices also shrinks to be in accordance with product demands and the trends of high integration, high performance, and low power consumption. Taking the double data rate-synchronous dynamic random access memory (DDR-DRAM) for an example, deep trench capacitor structures are widely utilized for a high density DRAM layout to improve integration.
Please refer to FIGS. 1 and 2. FIG. 1 is a schematic diagram showing a conventional checkerboard deep trench DRAM cell array layout. FIG. 2 is a schematic cross-sectional view taken along line I-I′ of FIG. 1, and further shows bit lines (hereinafter referred to as “BL”). The conventional checkerboard deep trench DRAM cell array 10 is characterized that the deep trench capacitors 11 in the memory cell array are arranged staggeredly in a checkerboard type. The bit lines (BL, shown in FIG. 2 but not in FIG. 1) orthogonally overlie the gate conductor lines (GC). Each deep trench capacitor 11 includes a single side buried strap (SSBS), as shown in FIG. 2. Each bit line is electrically connected to a source/drain region of a corresponding cell select transistor through a bit line contact (hereinafter referred to as “CB”) 12 on active areas 17.
In the conventional checkerboard deep trench DRAM cell array, all of the gate conductor lines are straight lines with a same width. Thus, under consideration to the limitation of the feature size of the manufacturing process, when the line width of the gate conductor lines and the distance between two adjacent gate conductor lines are designed to be as small as 1 feature size, the CB landing area between two gate conductor lines will be too narrow with respect to 60 nm or sub-60 nm manufacturing processes, and accordingly the process window of the dry etching will be small in a CB manufacturing process. This will cause a contact open issue, and CB tends to be damaged. If the transistor structure includes a recess gate channel structure, it is also affected by the minimized size.
The conventional layout structure includes components with respective sizes. For example, when the memory cell array is manufactured in 1 feature size (F), the line width of the gate conductor lines is 1 F, and the distance between two adjacent gate conductor lines is 1 F. Generally, the deep trench capacitors shift in a distance of 0.1 F toward one side of the gate conductor lines, and, as a result, the width B is 0.75 F, and the width C is 0.95 F. The spacers (not shown), which are typically disposed on the sidewalls of the gate conductor lines, generally have a thickness of 15 nm. In case 1 F equals 50 nm, the spacer has already occupied 0.3 F of 1 F. Thus, when the active areas with the width C, which is wider than the width B, are used as the areas for bit line contact, the width for the nominal landing area remains only in 0.35 F, which equals to 17.5 nm and is too narrow.
Such checkerboard deep trench DRAM cell array has a layout with narrow bit line contact areas in the 60 nm or sub-60 nm manufacturing process, such that the aspect ratio will be too high and the manufacture is not easy. Accordingly, when the contact hole is filled with conductive material, contact open issue tends to occur and the electric properties of the devices will be affected.
FIG. 3 shows another conventional deep trench DRAM cell array, a MINT (merged isolation and node trench) cell DRAM cell array using a low power. In the MINT cell DRAM cell array 20, deep trench capacitors 13 are disposed under passing word lines 15. Transistors 14 are electrically connected to storage nodes 16 of deep trench capacitors 13 through active areas 18. Active areas 19 are also included, which are electrically connected to contacts 22. Contacts 22 connect to bit lines (not shown) to read and write to storage nodes 16 through transistors 14. A wiggled word line layout has been proposed to increase the area of the bit line contact, as shown in FIG. 4. However, the photo process in manufacturing processes for such layout is difficult to carry out.
Therefore, there is still a need for a checkerboard deep trench DRAM cell array layout having high integration but without the aforesaid problems.